Hypervisors support execution of virtual machines running in computer systems and have multiple components (e.g., virtual machines, user worlds, virtual machine kernel, etc.) that share resources of the computer systems. Hypervisors are tailored to optimize the usage of the resources of the computer systems while complying with restrictions of the computer systems.
As part of transitioning execution control from one component to another, the hypervisor performs a context switch—storing and restoring component-specific state, such as memory and processor state. Context switches have a performance impact on a system that requires careful optimization and mitigation. Consequently, efficiently managing page tables, exception vectors (i.e., fixed memory addresses to which execution is directed in response to interrupts and other processor exceptions events), address space identifiers (ASID), and/or virtual machine identifiers (VMID) to optimize context switches across various hypervisor components noticeably improves the performance of the virtual machines and user worlds.
The implementation and accessibility of features, such as ASIDs, that each hypervisor component may leverage to streamline context switches varies based on the hardware architecture. Further, some hardware architectures provide multiple hierarchical privilege levels that each provide a different set of performance and resource tradeoffs and constraints for the components executing at the privilege level. Examples of such hardware architectures are the ARM®v7 and ARM®v8 (Instruction Set Architecture versions 7 and 8) hardware architectures, which are commercially available from ARM Holdings of Cambridge, United Kingdom. To perform efficient context switches in architectures with multiple hierarchical privilege levels, a strategy that judiciously assigns and manages the hypervisor components across the privilege levels is desirable.